The present disclosure herein relates to semiconductor devices and methods of fabricating semiconductor devices. A three-dimensional-integrated circuit (3D-IC) memory technique, as a technique for increasing memory capacity, denotes various techniques related to the three-dimensional arrangement of memory cells. Moreover, memory capacity may be increased through (1) a fine pattern technique and (2) a multi-level cell (MLC) technique, in addition to the 3D-IC memory technique. However, the fine pattern technique may be accompanied by high costs and the MLC technique may be limited to the number of bits per cell that can be increased. Accordingly, the 3D-IC technique may become a popular method for increasing memory capacity. The fine pattern and MLC techniques may also be developed independently from the 3D-IC technique, because memory capacity may be further increased when the fine pattern and MLC techniques are integrated with the 3D-IC technique.
A punch-and-plug technique has been proposed as one example of the 3D-IC technique. The punch-and-plug technique may include operations in which multilayer thin films are sequentially formed on a substrate and plugs penetrating the thin films are then formed. Because the memory capacity of a 3D memory device may be significantly increased without a significant increase in manufacturing costs when the punch-and-plug technique is used, this technique has received much attention.